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? 2011-2013 microchip technology inc. ds25010e-page 1 MCP7940N device selection table features: ? real-time clock/calendar (rtcc), battery backed: - hours, minutes, seconds, day of week, day, month and year - dual alarm with single output ? on-chip digital trimming/calibration: - range -127 to +127 ppm - resolution 1 ppm ? programmable open-drain output control: - clkout with 4 selectable frequencies - alarm output ? 64 bytes sram, battery backed ? automatic v cc switchover to v bat backup supply ? power-fail time-stamp for battery switchover ? low-power cmos technology: - dynamic current: 400 ? a max read - battery backup current: <700na @ 1.8v ? 100 khz and 400 khz compatibility ? esd protection >4,000v ? packages include 8-lead soic, tssop, 2x3 tdfn, msop ? pb-free and rohs compliant ? temperature ranges: - industrial (i): -40c to +85c - extended (e): -40c to +125c description: the MCP7940N series of low-power real-time clocks (rtc) uses digital timing compensation for an accurate clock/calendar, a programmable output control for versatility, a power sense circuit that automatically switches to the backup supply. using a low-cost 32.768 khz crystal, it tracks time using several internal registers. for communication, the MCP7940N uses the i 2 c? bus. the clock/calendar automatically adjusts for months with fewer than 31 days, including corrections for leap years. the clock operates in either the 24-hour or 12-hour format with an am/pm indicator and settable alarm(s) to the second, minute, hour, day of the week, date or month. using the programmable clkout, frequencies of 32.768, 8.192 and 4.096 khz and 1 hz can be generated from the external crystal. the device is fully accessible through the serial interface while v cc is between 1.8v and 5.5v, but can operate down to 1.3v for timekeeping and sram retention only. the rtc series of devices are available in the standard 8-lead soic, tssop, msop and 2x3 tdfn packages. package types part number sram (bytes) MCP7940N 64 x1 x2 v bat v ss v cc mfp scl sda 1 2 3 4 8 7 6 5 msop soic, tssop x1 x2 v bat v ss 1 2 3 4 8 7 6 5 v cc mfp scl sda tdfn x1 x2 v bat v ss mfp scl sda v cc 8 7 6 5 1 2 3 4 low-cost i 2 c? real-time clock/calendar with sram and battery switchover
MCP7940N ds25010e-page 2 ? 2011-2013 microchip technology inc. figure 1-1: typical operating circuit figure 1-2: schematic x1 x2 v bat v ss mfp scl sda rtcc sram time-stamp/ alarms i 2 c? oscillator v bat switch v cc MCP7940N x1 x2 v bat vss vcc mfp scl sda system v cc c1 note 1 r1 r2 cx1 cx2 x1 c2 r4 d1 bat suggested values: c1 cx1, cx2 c2 r1 r2,3 r4 d1 bat x1 100nf see text 100pf 10k 2.2k 1k schottky back-up supply 32.768 khz crystal (see text) mfp scl sda note 1 : a 100nf capacitor should be placed as close to the vcc pin on the device as possible. r3
? 2011-2013 microchip technology inc. ds25010e-page 3 MCP7940N 1.0 electrical characteristics absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................6.5v all inputs and outputs w.r.t. v ss ..........................................................................................................-0.6v to v cc +1.0v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature with power applied......................................................................................... .......-40c to +125c esd protection on all pins ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????????????????? ????????????????????????? 4 kv table 1-1: dc characteristics ? notice : stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. dc characteristics electrical characteristics: industrial (i): v cc = +1.8v to 5.5v t a = -40c to +85c extended (e): v cc = +1.8v to 5.5v t a = -40c to +125c param. no. sym. characteristic min. typ. max. units conditions ? scl, sda pins ? ? ? ? d1 v ih high-level input voltage 0.7 v cc ?v? d2 v il low-level input voltage ? 0.3 v cc 0.2 v cc vv cc = 2.5v to 5.5v d3 v hys hysteresis of schmitt trig- ger inputs (sda, scl pins) 0.05 v cc ?v ( note 1 ) d4 v ol low-level output voltage (mfp, sda) ?0.40vi ol = 3.0 ma @ v cc = 4.5v i ol = 2.1 ma @ v cc = 2.5v d5 i li input leakage current ? 1 ? av in = v ss or v cc d6 i lo output leakage current ? 1 ? av out = v ss or v cc d7 c in , c out pin capacitance (sda, scl and mfp) ?10pfv cc = 5.0v ( note 1 ) t a = 25c, f = 400 khz d8 i cc read operating current sram ?300 ? av cc = 5.5v, scl = 400 khz i cc write ? 400 ? av cc = 5.5v, scl = 400 khz d9 i ccs standby current ? 1 5 ? a ? a v cc = 5.5v, scl = sda = v cc (i-temp) v cc = 5.5v, scl = sda = v cc (e-temp) d10 ibat operating current ? 700 ? na v bat = 1.8v @ 25c, figure 2-1 iv cc ?5? ? av cc = 3.6v @ 25c, figure 2-2 ( note 2 ) d11 vtrip v bat change over 1.3 1.7 v 1.5v typical at t amb = 25c d12 vccft v cc fall time ( note 1 ) 300 ? ? sfrom v trip (max) to v trip (min) d13 vccrt v cc rise time ( note 1 ) 0? ? sfrom v trip (min) to v trip (max) d14 v bat v bat voltage range ( note 1 ) 1.3 5.5 v ? d15 cosc oscillator pin capacitance ?3?pf ( note 1 ) note 1: this parameter is periodically sampled and not 100% tested. 2: standby with oscillator running.
MCP7940N ds25010e-page 4 ? 2011-2013 microchip technology inc. table 1-2: ac characteristics ac characteristics electrical characteristics: industrial (i): v cc = +1.8v to 5.5v t a = -40c to +85c extended (e): v cc = +1.8v to 5.5v t a = -40c to +125c param. no. symbol characteristic min. max. units conditions 1f clk clock frequency ? ? 100 400 khz 1.8v ? v cc < 2.5v (i, e-temp) 2.5v ? v cc ? 5.5v (i, e-temp) 2t high clock high time 4000 600 ? ? ns 1.8v ? v cc < 2.5v (i, e-temp) 2.5v ? v cc ? 5.5v (i, e-temp) 3t low clock low time 4700 1300 ? ? ns 1.8v ? v cc < 2.5v (i, e-temp) 2.5v ? v cc ? 5.5v (i, e-temp) 4t r sda and scl rise time ( note 1 ) ? ? 1000 300 ns 1.8v ? v cc < 2.5v (i, e-temp) 2.5v ? v cc ? 5.5v (i, e-temp) 5t f sda and scl fall time ( note 1 ) ? ? 1000 300 ns 1.8v ? v cc < 2.5v (i, e-temp) 2.5v ? v cc ? 5.5v (i, e-temp) 6t hd : sta start condition hold time 4000 600 ? ? ns 1.8v ? v cc < 2.5v (i, e-temp) 2.5v ? v cc ? 5.5v (i, e-temp) 7t su : sta start condition setup time 4700 600 ? ? ns 1.8v ? v cc < 2.5v (i, e-temp) 2.5v ? v cc ? 5.5v (i, e-temp) 8t hd : dat data input hold time 0 ? ns 9t su : dat data input setup time 250 100 ? ? ns 1.8v ? v cc < 2.5v (i, e-temp) 2.5v ? v cc ? 5.5v (i, e-temp) 10 t su : sto stop condition setup time 4000 600 ? ? ns 1.8v ? v cc < 2.5v (i, e-temp) 2.5v ? v cc ? 5.5v (i, e-temp) 11 t aa output valid from clock ? ? 3500 900 ns 1.8v ? v cc < 2.5v (i, e-temp) 2.5v ? v cc ? 5.5v (i, e-temp) 12 t buf bus free time: time the bus must be free before a new transmission can start 4700 1300 ? ? ns 1.8v ? v cc < 2.5v (i, e-temp) 2.5v ? v cc ? 5.5v (i, e-temp) 13 t sp input filter spike suppression (sda and scl pins) ?50ns ( note 1 and note 2 ) note 1: not 100% tested. 2: the combined t sp and v hys specifications are due to new schmitt trigger inputs, which provide improved noise spike suppression. this eliminates the need for a t i specification for standard operation.
? 2011-2013 microchip technology inc. ds25010e-page 5 MCP7940N figure 1-3: bus timing data scl sda in sda out 5 7 6 13 3 2 89 11 d4 4 10 12
MCP7940N ds25010e-page 6 ? 2011-2013 microchip technology inc. 2.0 dc and ac characteristics graphs and charts figure 2-1: i bat vs. v bat figure 2-2: iv cc active vs. v cc @ 25c i bat (na) v bat (v) -40 0 25 65 85 1 1.5 2 2.5 3 3.5 4 1400 1300 1200 1100 1000 900 800 700 600 500 400 iv cc ( u a) v cc (v) 16 14 12 10 8 6 4 2 0 1.5 2.5 3.5 4.5 5.5
? 2011-2013 microchip technology inc. ds25010e-page 7 MCP7940N 3.0 pin descriptions the descriptions of the pins are listed in tab l e 3 - 1 . table 3-1: pin descriptions figure 3-1: device pinouts 3.1 serial data (sda) this is a bidirectional pin used to transfer addresses and data into and out of the device. it is an open-drain terminal, therefore, the sda bus requires a pull-up resistor to v cc (typically 10 k ? for 100 khz, 2 k ?? for 400 khz). for normal data transfer, sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions. 3.2 serial clock (scl) this input is used to synchronize the data transfer from and to the device. 3.3 x1, x2 external crystal pins. 3.4 mfp open-drain pin used for alarm and clock-out. 3.5 vbat input for backup supply to maintain rtcc and sram during the time when v cc is below v trip . pin name pin function vss ground sda bidirectional serial data scl serial clock x1 xtal input, external oscillator input x2 xtal output v bat battery backup input (3v typ) mfp multi-function pin vcc power supply x1 x2 v bat vss vcc mfp scl sda 1 2 3 4 8 7 6 5 soic/dfn/msop/tssop
MCP7940N ds25010e-page 8 ? 2011-2013 microchip technology inc. 4.0 i 2 c bus characteristics 4.1 i 2 c interface the MCP7940N supports a bidirectional 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. the bus has to be controlled by a master device which generates the start and stop conditions, while the MCP7940N works as slave. both master and slave can operate as transmitter or receiver but the master device determines which mode is activated. 4.1.1 bus characteristics the following bus protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined ( figure 4-1 ). 4.1.1.1 bus not busy (a) both data and clock lines remain high. 4.1.1.2 start data transfer (b) a high-to-low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 4.1.1.3 stop data transfer (c) a low-to-high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must end with a stop condition. 4.1.1.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one bit of data per clock pulse. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device. 4.1.1.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge signal after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable-low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into account. during reads, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave (MCP7940N) will leave the data line high to enable the master to generate the stop condition. figure 4-1: data transfer sequence on the serial bus address or acknowledge valid data allowed to change stop condition start condition scl sda (a) (b) (d) (d) (c) (a)
? 2011-2013 microchip technology inc. ds25010e-page 9 MCP7940N figure 4-2: acknowledge timing 4.1.2 device addressing and operation a control byte is the first byte received following the start condition from the master device ( figure 4-2 ). the control byte for accessing the sram and rtcc registers are set to ? 1101111 ?. the rtcc registers and the sram share the same address space. the last bit of the control byte defines the operation to be performed. when set to a ? 1 ? a read operation is selected, and when set to a ? 0 ? a write operation is selected. the next byte received defines the address of the data byte ( figure 4-3 ). the upper address bits are transferred first, followed by the least significant bits (lsb). following the start condition, the MCP7940N monitors the sda bus, checking the device type identifier being transmitted. upon receiving an ? 1101111 ? code, the slave device outputs an acknowledge signal on the sda line. depending on the state of the r/w bit, the MCP7940N will select a read or write operation. figure 4-3: address sequence bit assignments scl 9 8 7 6 5 4 3 2 1123 transmitter must release the sda line at this point allowing the receiver to pull the sda line low to acknowledge the previous eight bits of data. receiver must release the sda line at this point so the transmitter can continue sending data. data from transmitter data from transmitter sda acknowledge bit 1101 r/w x a 0 ?????? sram rtcc control byte address byte control code 111 x = don?t care
MCP7940N ds25010e-page 10 ? 2011-2013 microchip technology inc. 5.0 rtcc functionality the MCP7940N family is a highly integrated rtcc. on-board time and date counters are driven from a low- power oscillator to maintain the time and date. an integrated v cc switch enables the device to maintain the time and date and also the contents of the sram during a v cc power failure. 5.1 rtcc memory map the rtcc registers are contained in addresses 0x00h-0x1fh. 64 bytes of user-accessable sram are located in the address range 0x20-0x5f. the sram memory is a separate block from the rtcc control and configuration registers. all sram locations are battery-backed-up during a v cc power fail. unused locations are not accessible, MCP7940N will noack after the address byte if the address is out of range, as shown in the shaded region of the memory map in figure 5-1 . the shaded areas are not implemented and read as ? 0 ?. no error checking is provided when loading time and date registers. ? addresses 0x00h-0x06h are the rtcc time and date registers. these are read/write registers. care must be taken when accessing these registers while the oscillator is running. ? incorrect data can appear in the time and date registers if a write is attempted during the time frame where these internal registers are being incremented. the user can minimize the likeli- hood of data corruption by ensuring that any writes to the time and date registers occur before the contents of the second register reach a value of 0x59h. ? addresses 0x07h-0x09h are the device configu- ration and calibration. ? addresses 0x0ah-0x10h are the alarm 0 registers. these are used to set up the alarm 0, the interrupt polarity and the alarm 0 compare. ? addresses 0x11h-0x17h are the same as 0x0bh- 0x11h but are used for alarm 1. ? addresses 0x18h-0x1fh are used for the time- stamp feature. the detailed memory map is shown in ta b l e 5 - 1 . figure 5-1: memory map 0x00 0x06 time and date configuration and calibration alarm 0 alarm 1 time-stamp sram (64 bytes) 0x07 0x09 0x0a 0x10 0x11 0x17 0x18 0x1f 0x20 0x5f 0x60 0xff
? 2011-2013 microchip technology inc. ds25010e-page 11 MCP7940N table 5-1: rtcc memory map address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function range reset state 00h st 10 seconds seconds seconds 00-59 00h 01h 10 minutes minutes minutes 00-59 00h 02h 12/24 10 hour am/pm 10 hour hour hours 1-12 + am/pm 00 - 23 00h 03h oscon v bat vbaten day day 1-7 01h 04h 10 date date date 01-31 01h 05h lp 10 month month month 01-12 01h 06h 10 year year year 00-99 01h 07h out sqwe alm1 alm0 extosc rs2 rs1 rs0 control reg. 80h 08h calibration calibration 00h 09h reserved ? do not use 00h 0ah 10 seconds seconds seconds 00-59 00h 0bh 10 minutes minutes minutes 00 - 59 00h 0ch 12/24 10 hour am/pm 10 hours hour hours 1-12 + am/pm 00-23 00h 0dh alm0pol alm0c2 alm0c1 alm0c0 alm0if day day 1-7 01h 0eh 10 date date date 01-31 01h 0fh 10 month month month 01-12 01h 10h reserved ? do not use reserved 01h 11h 10 seconds seconds seconds 00-59 00h 12h 10 minutes minutes minutes 00-59 00h 13h 12/24 10 hour am/pm 10 hours hour hours 1-12 + am/pm 00-23 00h 14h alm1pol alm1c2 alm1c1 alm1c0 alm1if day day 1-7 01h 15h 10 date date date 01-31 01h 16h 10 month month month 01-12 01h 17h reserved ? do not use reserved 01h 18h 10 minutes minutes 00h 19h 12/24 10 hour am/pm 10 hours hour 00h 1ah 10 date date 00h 1bh day 10 month month 00h 1ch 10 minutes minutes 00h 1dh 12/24 10 hour am/pm 10 hours hour 00h 1eh 10 date date 00h 1fh day 10 month month 00h
MCP7940N ds25010e-page 12 ? 2011-2013 microchip technology inc. 5.1.1 rtcc register addresses 0x00h ? contains the bcd seconds and 10 seconds. the range is 00 to 59. bit 7 in this register is used to start or stop the on-board crystal oscillator. setting this bit to a ? 1 ? starts the oscillator and clearing this bit to a ? 0 ? stops the on-board oscillator. 0x01h ? contains the bcd minutes and 10 minutes. the range is 00 to 59. 0x02h ? contains the bcd hour in bits 3:0. bits 5:4 contain either the 10 hour in bcd for 24-hour format or the am/pm indicator and the 10-hour bit for 12-hour format. bit 5 determines the hour format. setting this bit to ? 0 ? enables 24-hour format, setting this bit to ? 1 ? enables 12-hour format. 0x03h ? contains the bcd day. the range is 1-7. additional bits are also used for configuration and status. ? bit 3 is the vbaten bit. if this bit is set, the internal circuitry is connected to the v bat pin when v cc fails. if this bit is ? 0 ? then the v bat pin is disconnected and the only current drain on the external battery is the v bat pin leakage. ? bit 4 is the v bat bit. this bit is set by hardware when the v cc fails and the v bat is used to power the oscillator and the rtcc registers. this bit is cleared by software. clearing this bit will also clear all the time-stamp registers. ? bit 5 is the oscon bit. this is set and cleared by hardware. if this bit is set, the oscillator is running, if cleared, the oscillator is not running. this bit does not indicate that the oscillator is running at the correct frequency. the rtcc will wait 32 oscillator cycles before the bit is set. the rtcc will wait roughly 32 clock cycles to clear this bit. 0x04h ? contains the bcd date and 10 date. the range is 01-31. bits 5:4 contain the 10?s date and bits 4:0 contain the date. 0x05h ? contains the bcd month. bit 4 contains the 10 month. bit 5 is the leap year bit, which is set during a leap year and is read-only. 0x06h ? contains the bcd year and 10 year. the range is 00-99. 0x07h ? is the control register. ? bit 7 is the out bit. this sets the logic level on the mfp when not using this as a square wave output. ? bit 6 is the sqwe bit. setting this bit enables the divided output from the crystal oscillator. ? bits 5:4 determine which alarms are active. - 00 ? no alarms are active - 01 ? alarm 0 is active - 10 ? alarm 1 is active - 11 ? both alarms are active ? bit 3 is the extosc enable bit. setting this bit will allow an external 32.768 khz signal to drive the rtcc registers eliminating the need for an external crystal. ? bit 2:0 sets the internal divider for the 32.768 khz oscillator to be driven to the mfp. the duty cycle is 50%. the output is responsive to the calibration register. the following frequencies are available: - 000 ? 1 hz - 001 ? 4.096 khz - 010 ? 8.192 khz - 011 ? 32.768 khz - 1xx enables the cal output function. cal output appears on mfp if sqwe is set (64 hz nominal). see section 5.2.1 ?calibration? for more details. 0x08h is the calibration register. this is an 8-bit register that is used to add or subtract clocks from the rtcc counter every minute. the msb is the sign bit and indicates if the count should be added or subtracted. the remaining 7 bits, with each bit adding or subtracting 2 clocks, give the user the ability to add or subtract up to 254 clocks per minute. 0x0ah-0x0fh and 0x11-0x16h are the alarm 0 and alarm 1 registers. the bits are the same as the rtcc bits with the following differences: locations 0x10h and 0x17h are reserved and should not be used to allow for future device compatibility. 0x0dh/0x14h has additional bits for alarm configu- ration. ? almxpol: this bit specifies the level that the mfp will drive when the alarm is triggered. alm2pol is a copy of alm1pol. the default state of the mfp when used for alarms is the inverse of alm1pol. ? almxif: this is the alarm interrupt fag. this bit is set in hardware if the alarm was triggered. the bit is cleared in software. ? almxc2:0: these configuration bits determine the alarm match. the logic will trigger the alarm based on one of the following match conditions: note: the rtcc counters will continue to increment during the calibration. 000 ? seconds match
? 2011-2013 microchip technology inc. ds25010e-page 13 MCP7940N ? the 12/24-hour bits 0xch.6 and 0x13h.6 are cop- ies of the bit in 0x02h.6. the bits are read-only. 0x18h-0x1bh are used for the timesaver function. these registers are loaded at the time when v cc fails and the rtcc operates on the v bat . the v bat bit is also set at this time. these registers are cleared when the v bat bit is cleared in software. 0x1ch-0x1fh are used for the timesaver function. these registers are loaded at the time when v cc is restored and the rtcc switches to v dd . these registers are cleared when the v bat bit is cleared in software. 5.2 features 5.2.1 calibration the MCP7940N utilizes digital calibration to correct for inaccuracies of the input clock source (either external or crystal). calibration is enabled by setting the value of the calibration register at address 08h. calibration is achieved by adding or subtracting a number of input clock cycles per minute in order to achieve ppm level adjustments in the internal timing function of the MCP7940N. the msb of the calibration register is the sign bit, with a ? 1 ? indicating subtraction and a ? 0 ? indicating addition. the remaining seven bits in the register indicate the number of input clock cycles (multiplied by two) that are subtracted or added per minute to the internal timing function. the internal timing function can be monitored using the mfp open-drain output pin by setting bit [6] (sqwe) and bits [2:0] (rs2, rs1, rs0) of the control register at address 07h. note that the mfp output waveform is disabled when the MCP7940N is running in v bat mode. with the sqwe bit set to ? 1 ?, there are two methods that can be used to observe the internal timing function of the MCP7940N: a. rs2 bit set to ? 0 ? with the rs2 bit set to ? 0 ?, the rs1 and rs0 bits enable the following internal timing signals to be output on the mfp pin: the frequencies listed in the table presume an input clock source of exactly 32.768 khz. in terms of the equivalent number of input clock cycles, the table becomes: with regards to the calibration function, the calibration register setting has no impact upon the mfp output clock signal when bits rs1 and rs0 are set to ? 11 ?. the setting of the calibration register to a non-zero value (i.e., values other than 00h or 80h) enables the calibration function which can be observed on the mfp output pin. the calibration function can be expressed in terms of the number of input clock cycles added/subtracted from the internal timing function. 001 ? minutes match 010 ? hours match (takes into account 12/24 hour) 011 ? matches the current day, interrupt at 12.00.00 a.m. example: 12 midnight on 100 ?date 101 ? reserved 110 ? reserved 111 ? seconds, minutes, hour, day, date, month note: it is strongly recommended that the timesaver function only be used when the oscillator is running. this will ensure accurate functionality. rs2 rs1 rs0 output signal 000 1 hz 001 4.096 khz 010 8.192 khz 011 32.768 khz rs2 rs1 rs0 output signal 000 32768 001 8 010 4 011 1
MCP7940N ds25010e-page 14 ? 2011-2013 microchip technology inc. with bits rs1 and rs0 set to ? 00 ?, the calibration function can be expressed as: since the calibration is done once per minute (i.e., when the internal minute counter is incremented), only one cycle in sixty of the mfp output waveform is affected by the calibration setting. also note that the duty cycle of the mfp output waveform will not necessarily be at 50% when the calibration setting is applied. with bits rs1 and rs0 set to ? 01 ? or ? 10 ?, the calibration function can not be expressed in terms of the input clock period. in the case where the msb of the calibration register is set to ? 0 ?, the waveform appearing at the mfp output pin will be ?delayed?, once per minute, by twice the number of input clock cycles defined in the calibration register. the mfp waveform will appear as: figure 5-2: rs1 and rs0 with and without calibration in the case where the msb of the calibration register is set to ? 1 ?, the mfp output waveforms that appear when bits rs1 and rs0 are set to ? 01 ? or ? 10 ? are not as responsive to the setting of the calibration register. for example, when outputting the 4.096 khz waveform (rs1, rs0 set to ? 01 ?), the output waveform is generated using only eight input clock cycles. consequently, attempting to subtract more than eight input clock cycles from this output does not have a meaningful effect on the resulting waveform. any effect on the output will appear as a modification in both the frequency and duty cycle of the waveform appearing on the mfp output pin. b.rs2 bit set to ? 1 ? with the rs2 bit set to ? 1 ?, the following internal timing signal is output on the mfp pin: the frequency listed in the table presumes an input clock source of exactly 32.768 khz. in terms of the equivalent number of input clock cycles, the table becomes: unlike the method previously described, the calibration setting is continuously applied and affects every cycle of the output waveform. this results in the modulation of the frequency of the output waveform based upon the setting of the calibration register. using this setting, the calibration function can be expressed as: since the calibration is done every cycle, the frequency of the output mfp waveform is constant. t output = (32768 +/- (2 * calreg)) t input where: t output = clock period of mfp output signal t input = clock period of input signal calreg = decimal value of calibration register setting and the sign is determined by the msb of calibration register. delay rs2 rs1 rs0 output signal 1 x x 64.0 hz rs2 rs1 rs0 output signal 1 x x 512 t output = (2 * (256 +/- (2 * calreg))) t input where: t output = clock period of mfp output signal t input = clock period of input signal calreg = decimal value of the calibration register setting, and the sign is determined by the msb of the calibration register.
? 2011-2013 microchip technology inc. ds25010e-page 15 MCP7940N 5.2.2 mfp pin 7 is a multi-function pin and supports the following functions: ? use of the out bit in the control register for single bit i/o ? alarm outputs ? available in v bat mode ? fout mode ? driven from a fosc divider ? not available in v bat mode the internal control logic for the mfp is connected to the switched internal supply bus, this allows operation in v bat mode. the alarm output is the only mode that operates in v bat mode, other modes are suspended. 5.2.3 vbat the MCP7940N features an internal switch that will power the clock and the sram. in the event that the v cc supply is not available, the voltage applied to the v bat pin serves as the backup supply. a low-value series resistor is recommended between the external battery and the v bat pin to limit the current to the internal switch circuit. the v bat trip point is the point at which the internal switch operates the device from the v bat supply and is typically 1.5v (v trip specification d12) typical. when v dd falls below 1.5v the system will continue to operate the rtcc and sram using the v bat supply. the following conditions apply: if the v bat feature is not being used, the v bat pin must be connected to gnd. for more information on v bat conditions see application note an1365, ? rtcc best practices ? (ds01365). table 5-2: supply condition read/write access powered by v cc < v trip , v cc < v bat no v bat v cc > v trip , v cc < v bat yes v cc v cc > v trip , v cc > v bat yes v cc
MCP7940N ds25010e-page 16 ? 2011-2013 microchip technology inc. 5.2.4 crystal specs the MCP7940N has been designed to operate with a standard 32.768 khz tuning fork crystal. the on-board oscillator has been characterized to operate with a crystal of maximum esr of 70k ohms. crystals with a comparable specification are also suit- able for use with the MCP7940N. the table below is given as design guidance and a starting point for crystal and capacitor selection. equation 5-1: the following must also be taken into consideration: ? pin capacitance (to be included in cx2 and cx1) ? stray board capacitance the recommended board layout for the oscillator area is shown in figure 5-3 . this actual board shows the crystal and the load capacitors. in this example, c2 is cx1, c3 is cx2 and the crystal is designated as y1. figure 5-3: board layout gerber files are available from www/microchip.com/rtcc . it is required that the final application should be tested with the chosen crystal and capacitor combinations across all operating and environmental conditions. please also consult with the crystal specification to observe correct handling and reflow conditions and for information on ideal capacitor values. for more information please see application note an1365, ? rtcc best practices ? (ds01365). manufacturer part number crystal capacitance cx1 value cx2 value micro crystal cm7v-t1a 7pf 10pf 12pf citizen cm200s-32.768kdzb-ut 6pf 10pf 8 pf please work with your crystal vendor. c load cx2 cx1 ? cx2 cx1 + ----------------------------- c stray + =
? 2011-2013 microchip technology inc. ds25010e-page 17 MCP7940N 5.2.5 power-fail time-stamp the mcp7941x family of rtcc devices feature a power-fail time-stamp feature. this feature will store the time at which v cc crosses the v trip voltage and is shown in figure 5-4 . to use this feature, a v bat supply must be present and the oscillator must also be running. there are two separate sets of registers that are used to record this information: ? the first set, located at 0x18h through 0x1bh, is loaded at the time when v cc falls below v trip and the rtcc operates on the v bat . the v bat (register 0x03h bit 4) bit is also set at this time. ? the second set of registers, located at 0x1ch through 0x1fh, is loaded at the time when v cc is restored and the rtcc switches to v cc . the power-fail time-stamp registers are cleared when the v bat bit is cleared in software. figure 5-4: power-fail graph v cc v trip(max) v trip(min) v ccft v ccrt power-down power-up time-stamp time-stamp
MCP7940N ds25010e-page 18 ? 2011-2013 microchip technology inc. 6.0 on board memory the MCP7940N has battery-backed sram. the sram is arranged as 64 x 8 bytes and is retained when the v cc supply is removed, provided the v bat supply is present and enabled. 6.1 sram figure 6-1: sram/rtcc byte write figure 6-2: sram/rtcc multiple byte write the 64 bytes of user sram are at location 0x20h and can be accessed during an rtcc update. upon por the sram will be in an undefined state. bus activity master sda line bus activity s t a r t control byte address byte data s t o p a c k a c k a c k s 1101 0 1 11 p x bus activity master sda line bus activity s t a r t control byte address byte data byte 0 s t o p a c k a c k a c k data byte n a c k s 1101 0 111 p x note: entering an address past 5f for an sram operation will result in the MCP7940N not acknowledging the address.
? 2011-2013 microchip technology inc. ds25010e-page 19 MCP7940N 6.2 rtcc/sram 6.2.1 sram byte write following the start condition from the master, the control code and the r/w bit (which is a logic low) are clocked onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the MCP7940N. after receiving another acknowledge signal from the MCP7940N, the master device transmits the data word to be written into the addressed memory location. the MCP7940N acknowledges again and the master generates a stop condition. after a byte write command, the internal address counter will point to the address location following the one that was just written. figure 6-3: sram byte write 6.2.2 read operation read operations are initiated in the same way as write operations with the exception that the r/w bit of the control byte is set to one. there are three basic types of read operations: current address read, random read, and sequential read. 6.2.2.1 current address read the MCP7940N contains an address counter that maintains the address of the last word accessed, internally incremented by one. therefore, if the previous read access was to address n (n is any legal address), the next current address read operation would access data from address n + 1. upon receipt of the control byte with r/w bit set to one, the MCP7940N issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition and the MCP7940N discontinues transmission ( figure 6-4 ). figure 6-4: current address read 6.2.2.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, first the word address must be set. this is done by sending the word address to the MCP7940N as part of a write operation (r/w bit set to ? 0 ?). after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. then, the master issues the control byte again but with the r/w bit set to a one. the MCP7940N will then issue an acknowledge and transmit the 8-bit data word. the master will not acknowledge the transfer but it does generate a stop condition which causes the MCP7940N to discontinue transmission ( figure 6-5 ). after a random read command, the internal address counter will point to the address location following the one that was just read. note: addressing undefined sram locations will result in the MCP7940N not acknowledging the address. bus activity master sda line bus activity s t a r t control byte address byte data s t o p a c k a c k a c k s 1101 0 1 11 p x x = don?t care for 1k devices bus activity master sda line bus activity p s s t o p control byte s t a r t data a c k n o a c k 10 11 1 byte 111
MCP7940N ds25010e-page 20 ? 2011-2013 microchip technology inc. 6.2.2.3 sequential read sequential reads are initiated in the same way as a random read except that after the MCP7940N transmits the first data byte, the master issues an acknowledge as opposed to the stop condition used in a random read. this acknowledge directs the MCP7940N to transmit the next sequentially addressed 8-bit word ( figure 6-6 ). following the final byte transmitted to the master, the master will not generate an acknowledge but will generate a stop condition. to provide sequential reads, the MCP7940N contains an internal address pointer which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. the internal address pointer will automat- ically roll over to the start of the block. figure 6-5: random read figure 6-6: sequential read bus activity master sda line bus activity a c k n o a c k a c k a c k s t o p s t a r t control byte address byte control byte data byte s t a r t s 1101 0 111 s 1010 1 p bus activity master sda line bus activity control byte data n data n + 1 data n + 2 data n + x n o a c k a c k a c k a c k a c k s t o p p
? 2011-2013 microchip technology inc. ds25010e-page 21 MCP7940N 7.0 packaging information 7.1 package marking information 8-lead soic (3.90 mm) example: xxxxxt xxyyww nnn 8-lead tssop example: 7940ni sn 1133 13f 8-lead msop example: xxxx tyww nnn xxxxx ywwnnn 940n i133 13f 7940ni 13313f 3 e 8-lead 2x3 tdfn xxx yww nn aav 133 13 example: part number 1st line marking codes tssop msop tdfn MCP7940N 940n 7940nt aav note: t = temperature grade nn = alphanumeric traceability code legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
MCP7940N ds25010e-page 22 ? 2011-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011-2013 microchip technology inc. ds25010e-page 23 MCP7940N note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
MCP7940N ds25010e-page 24 ? 2011-2013 microchip technology inc.
? 2011-2013 microchip technology inc. ds25010e-page 25 MCP7940N d n e e1 note 1 12 b e c a a1 a2 l1 l
MCP7940N ds25010e-page 26 ? 2011-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011-2013 microchip technology inc. ds25010e-page 27 MCP7940N note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
MCP7940N ds25010e-page 28 ? 2011-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011-2013 microchip technology inc. ds25010e-page 29 MCP7940N note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
MCP7940N ds25010e-page 30 ? 2011-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011-2013 microchip technology inc. ds25010e-page 31 MCP7940N note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
MCP7940N ds25010e-page 32 ? 2011-2013 microchip technology inc.
? 2011-2013 microchip technology inc. ds25010e-page 33 MCP7940N d n e e1 note 1 12 b e c a a1 a2 l1 l
MCP7940N ds25010e-page 34 ? 2011-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011-2013 microchip technology inc. ds25010e-page 35 MCP7940N appendix a: revision history revision a (04/2011) original release of this document. revision b (09/2011) ? added figure 1-2 ? added parameter d15 to tab le 1 -1 ? added section 3.3 ?x1, x2? , section 3.4 ?mfp? , section 3.5 ?vbat? ? added figure 5-1 ? updated section 5.2.3 ?vbat? , section 5.2.4 ?crystal specs? , section 5.2.5 ?power-fail time-stamp? . revision c (12/2011) added dc/ac char. charts. revision d (11/2012) added extended temp. revision e (01/2013) revised table 1-2: ac characteristics; temperature range.
MCP7940N ds25010e-page 36 ? 2011-2013 microchip technology inc. notes:
? 2011-2013 microchip technology inc. ds25010e-page 37 MCP7940N the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
MCP7940N ds25010e-page 38 ? 2011-2013 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds25010e MCP7940N 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2011-2013 microchip technology inc. ds25010e-page 39 MCP7940N product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . not every possible ordering combination is listed below. part no. x /xx package temperature range device device: MCP7940N = 1.8v - 5.5v i 2 c? serial rtcc MCP7940Nt= 1.8v - 5.5v i 2 c? serial rtcc (tape and reel) temperature range: i = -40c to +85c e = -40c to +125c (sn, ms package only) package: sn = 8-lead plastic small outline (3.90 mm body) st = 8-lead plastic thin shrink small outline (4.4 mm) ms = 8-lead plastic micro small outline mny (1) = 8-lead plastic dual flat, no lead examples: a) MCP7940N-i/sn: industrial tempera- ture, soic package. b) MCP7940Nt-i/sn: industrial tempera- ture, soic package, tape and reel. c) MCP7940Nt-i/mny: industrial tempera- ture, tdfn package. d) MCP7940N-i/ms: industrial temperature msop package. e) MCP7940N-i/st: industrial temperature, tssop package. f) MCP7940Nt-i/st: industrial temperature, tssop package, tape and reel. g) MCP7940N-e/sn: extended temperature, soic package. note 1: ?y? indicates a nickel palladium gold (nipdau) finish.
MCP7940N ds25010e-page 40 ? 2011-2013 microchip technology inc. notes:
? 2011-2013 microchip technology inc. ds25010e-page 41 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2011-2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620769546 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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